VMIACC-5595-208 反射内存集线器组件 用于与通用电气发那科/ VMIC 5565系列

VMIACC-5595-208

The GE Fanuc / VMIC VMIACC-5595 Gb/s Reflective Memory Hub Assembly is a managed hub designed to operate with the GE Fanuc / VMIC 5565 family of Reflective Memory real-time network products. The Reflective Memory hub can automatically bypass ports when it detects a loss of signal or the loss of valid synchronization patterns, allowing the other nodes in the network to remain operational. Since the optical ports are implemented with small form factor pluggable (SFP) transceivers, only the required ports need to be populated. The VMIACC-5595 SFP transceivers can be a combination of either multimode (short distance) or single-mote (long-distance) transceivers. This feature permits a cost saving in small networks as well as system optimization. For larger networks, several VMIACC-5595 assemblies can be cascaded, permitting a managed hub aray with up to 256 nodes. Each port regenerates the serial optical signal, eliminating the problems with insertion losses and cable attenuation. Signal regeneration also reduces jitter. The RS232 port gives the ability to monitor and control the Reflective Memory network through a simple PC serial port. The Ethernet port feature allows the user to monitor and control the hub from great distances through a local area network (LAN) or via a Web browser

The VMIACC-5595 can be configured as a 19-inch 1U rack-mountable enclosure or as a desktop enclosure. The universal power supply permits operation with nearly any international power standard.

The VMIACC-5595 automatically bypasses ports when the absence of valid synchronization patterns is detected. Three LEDs, adjacent to each port, provide a visual indication of the port status. Additional status indications and modes of operation are available through either the serial port or the Ethernet port.

Status information includes the detection of installed transceivers, the detection of signal (light), the detection of valid synchronization patterns, and the port operation speed (2Gb/s). Control registers allow the channel bypass to be based on the absence of a single valid synchronization pattern or multiple synchronization patterns. A bypass can also be based simply on the loss of a signal (light). In addition, each port can be manually forced either active or bypassed regardless of the status indicators.